Patent Literature 1 (see FIG. 38) discloses a gate driver used in a liquid crystal display device which gate driver includes a shift register having a plurality of stages. Each of the plurality of stages has (i) a set-reset type flip-flop having an initial terminal (INI) and (ii) a gate circuit including an analog switch 43 and an n-channel transistor 44. Moreover, a clock signal CK is supplied to the analog switch 43, a source of the transistor 44 is connected to a VSS, and an output signal On of each of the stages is supplied to a corresponding scanning signal line. In the configuration, when a power supply of the liquid crystal display device is turned on, output signals (On−1, On, On+1, and the like) of all the stages sequentially become active after each delay by causing a start pulse ST to become active while the clock signal CK is being fixed to active (see FIG. 39). This makes it possible to simultaneously select all the scanning signal lines so that a Vcom (common electrode electric potential) is written into all pixels.